There are many applications where a wafer probe is used to connect an IC device to a printed circuit board (PCB) so that the electrical connection is made in a separable manner. As illustrated in FIG. 1, a wafer probe 20 in a test system 22 may have a plurality of probe members 24 that connect terminals 26 (or contact pads) on an IC device 28 to corresponding terminals 30 (or contact pads) on a PCB 32. The probe members 24 are held against the terminals 26 on the IC device 28 by applying a load 34 (or force) that maintains intimate contact and reliable connection during testing. No permanent connection is required such that the IC device 28 can be removed or replaced without a need to reflow solder connections.
The probe members 24 in the wafer probe 20 have at least two interface points for every probe member 24, a first interface 36 with the IC device 28 and a second interface 38 with the PCB 32. When the wafer probe is used 20 to connect to the IC device 28, there may be an assumption that the connection point for each terminal 26 is reliable. In the event the system is powered and the function of the IC device 28 is not as expected, any one of many connection points at the interfaces 36, 38 may be a cause of an error.
If the IC device 28 is removed and replaced and the issue is resolved, then a conclusion can be drawn that all of the other components in the test system 22 are connected and functioning properly. In the event the error is not resolved or another issue is introduced, the user must systematically sort through the various components and connections within the test system 22 to resolve the issue. In many cases, the wafer probe 20 may be a source of error due to the number of connections at the interfaces 36, 38 and the potential for at least one of those connections to be improperly positioned. A typical method to identify and resolve a wafer probe connection error is to replace the wafer probe 20 with another new wafer probe, or place the wafer probe 20 on an interface known to function properly to attempt to determine if the wafer probe 20 is the source of the error. If the new wafer probe functions properly, then the initial wafer probe 20 can be deemed the source of the error. If the new wafer probe does function properly, then the issue is not resolved because the issue may be common or related to how the wafer probe 20 interfaces to the IC device 28 or to the PCB 32. This systematic troubleshooting process can be extremely time consuming and can cause major delays, and can impact the ability to continue testing IC devices.
There are several limitations to traditional methods of identifying and resolving wafer probe connection problems. The common method of replacing the wafer probe 20 with another is typically the first avenue, and requires that additional wafer probes 20 are available. Also, a successful result depends entirely on whether the issue is isolated to the initial wafer probe 20. This method can identify if there is an anomaly with the initial wafer probe 20 such as a damaged contact or poor connection. In the event the new wafer probe 20 does not produce desired results, further investigation is required. There may be a problem that is common to the wafer probes generally, and additional investigation is needed to determine if the source of the error remains with the wafer probe 20 or if the issue is elsewhere.
Another method of identifying and resolving wafer probe 20 connection errors may involve creating an external validation vehicle such as a PCB that mimics the system board. This method can be more determinant than an “in the system” approach such as replacing the wafer probe. The wafer probe interfaces 36, 38 can be isolated and if there is an issue with the group of contacts or with specific contacts the issue can be readily identified. A limitation of this method, however, can include that it requires that these external tools be created ahead of time so they are available if and when they are needed, which would result in additional effort and expense that is wasted if the wafer probe performs as expected.
Establishing these tools ahead of time can provide confidence that the wafer probe is functioning properly and, in the end, reduce effort because the user can trust that the wafer probe is working. However, there is some risk that the external tools may not match the actual system circuit board precisely in form and/or function, and that issues that are not present on the external tools may be present on the system PCB. Another limitation is that it can be difficult to mimic the terminal pattern of the IC device being tested due to the fine feature size and pitch. Still another limitation with this method may be the adverse consequences of failing to produce these external tools ahead of time, since the lead time to design and produce these tools can be long. Still another limitation is that an external circuit board or test system may not precisely match the make-up of the actual system, and/or utilize an exact IC device. Typically, a surrogate IC device is used to simulate the actual IC device and a surrogate PCB is used to simulate the system PCB. The surrogate IC device and surrogate PCB may manifest issues different from or not present in the actual IC device and surrogate PCB. Similarly, the surrogates may not manifest issues present in the actual IC device and PCB. Accordingly, problems may go undetected.
In the event these methods do not identify the problem, the actual IC device can be soldered to the site intended for the wafer probe so that the wafer probe can be eliminated from the equation. However, this method defeats the advantages of using a water probe, including eliminating the desired separability.